IEEE standard 1149.1 (JTAG) provides boundary scan architecture and a serial test bus for integrated (ICs). Multiple ICs may be connected together on the test bus to allow accessing all ICs together during board level testing. Boards equipped with these JTAG ICs can be connected at the backplane level using two fundamental access schemes. The first scheme is to serially daisy-chain boards together to allow all boards to be accessed simultaneously. The second scheme is to provide each board with an addressable interface such that boards may be accessed individually. The first scheme suffers from the disadvantage that if one board is removed from the backplane, the access to other boards is disabled. The second scheme overcomes this problem by using an addressable scheme to access remaining boards in the backplane. Examples of the second scheme are described in detail in U.S. Pat. No. 6,363,443, which patent is incorporated herein by reference.
Some boards are preferably designed by partitioning subsets of ICs onto individual scan paths. This partitioning allows accessing subset groups of ICs separately, which offers several advantages. One advantage is that ICs that are capable of being accessed at higher JTAG test bus clock rates can be included in one group, while ICs that operate at slower test bus clock rates may be placed in another group. Thus test bus speed binning is possible. Another advantage in partitioning ICs onto separate scan paths is that it allows accessing a first scan path group to initiate a self test operation, then, while that group operates the self test, accessing another scan path group to start testing of that IC group. Still another advantage is that some ICs may include emulation and debug features that are accessible by the JTAG test bus. Being able to place these types of ICs in a group separate from other ICs leads to improvements in execution efficiency of JTAG based debug and emulation operations.
The Addressable Shadow Port (ASP) described in U.S. Pat. No. 6,363,443 uses a Shadow Protocol that is transmitted transparently over the JTAG test bus. At the backplane level, the Shadow Protocol is used to send an address over the backplane test bus to enable one of a plurality of board resident ASPs. Once enabled, the ASP of the addressed board allows the backplane JTAG test bus to communicate to the ICs of the addressed board. If the board has multiple scan paths to allow accessing ICs in the above mentioned grouping style, an ASP and an associate address would be required for each scan path group. Thus a board with multiple scan paths would require multiple ASPs each with a distinct address.
Linker circuits are known which allow augmentation of a system's primary scan path with secondary scan paths which can be individually selected for inclusion in the primary scan path. These are configured by loading a register with instructions by placing it in the scan path.